1. Field of the Invention
The present invention relates to methods for manufacturing cells of an electrically erasable and programmable non-volatile memory or EEPROM cells and to the memory cells obtained with such methods.
2. Discussion of the Related Art
An EEPROM cell generally comprises a selection element and a storage element. As an example, the selection element corresponds to a conventional single-gate MOS transistor and the storage element corresponds to a dual-gate MOS transistor comprising a floating gate covered with a control gate. The floating gate insulator comprises a thinned portion at the level of the dual-gate transistor drain which forms a tunnel window. The tunnel window is thin enough to enable tunneling, of carriers between the floating gate and the underlying channel.
The operation of such a memory cell is the following. An erasing operation in the memory cell is performed by turning on the selection transistor, by setting to 0 volt the drain and the source of the dual-gate transistor, and by setting the control gate of the dual-gate transistor to a given voltage. This causes the passing of charges (electrons) from the drain to the floating gate of the dual-gate transistor through the tunnel window and the storage of charges in the floating gate. A write operation in the memory is performed by turning on the selection transistor, by applying a write voltage between the drain and the source of the dual-gate transistor and by maintaining the control gate of the dual-gate transistor at 0 volt. This causes the evacuation of the charges stored in the floating gate through the tunnel window. A read operation is performed by turning on the selection transistor, by applying a read voltage, smaller than the write voltage, between the drain and the source of the dual-gate transistor, and by setting the control gate of the dual-gate transistor to a given voltage. The intensity of the current crossing the dual-gate transistor is representative of the presence or of the absence of charges in the floating gate.
A disadvantage of a conventional EEPROM cell is that a leakage of the charges stored in the floating gate of the storage element, which tend to escape through the tunnel window, can be observed. Indeed, the thickness of the floating gate insulator at the level of the tunnel window is generally smaller than some ten nanometers and the charges are mainly stored in the floating gate close to the tunnel window so that charges stored in the floating gate can cross the tunnel window by mere thermal agitation.
U.S. patent application Ser. No. 11/525,529, which is incorporated herein by reference, describes a method for manufacturing an EEPROM cell enabling improving the charge retention in the floating gate of the storage cell. For this purpose, the floating gate comprises an N-type doped region, at the level of a thick portion of the floating gate insulator, surrounded with P-type doped regions. The charges injected into the floating gate tend to be stored in the N-type region which is distant from the tunnel window. Leakage risks are thus decreased, since charges are stored at the level of a thick oxide portion.
However, the forming of the N- and P-type doped regions has disadvantages. Indeed, the P-type doped regions are generally formed by a step of implantation of P-type dopants, such as boron, into the floating gate which is previously N-type doped. The diffusion of dopant elements from the floating gate into the substrate can be observed during subsequent anneal steps. This tends to modify the dopant concentration profiles in the substrate, which is not desirable.